Application of a two-layer planarization process to VLSI intermetal dielectric and trench isolation processes

Author

Sheldon, D.J. ; Gruenschlaeger, C.W. ; Kammerdiner, L. ; Henis, N.B. ; Kelleher, P. ; Hayden, J.D.

Author_Institution

INMOS Corp., Colorado Springs, CO, USA

Volume

1

Issue

4

fYear

1988

Firstpage

140

Lastpage

146

Abstract

The application of a novel planarization process using a sacrificial fill layer of photoresist is presented. The process is shown to solve the planarization problems encountered in both intermetal dielectric for a 1.2 mu m 256 K SRAM technology and trench isolation for a0.8- mu m 1M SRAM technology. The process is a simple extension of the standard dielectric etch-back scheme. A discussion of how to precisely quantify circuit planarization using well-known techniques is also presented. This information can then be adapted for statistical quality control purposes.<>

Keywords

VLSI; integrated circuit technology; integrated memory circuits; random-access storage; 0.8 micron; 1 Mbit; 1.2 micron; 256 kbit; RBOX process; SRAM technology; VLSI; dielectric etch-back scheme; intermetal dielectric; memory device fabrication; photoresist; sacrificial fill layer; static RAM; statistical quality control; trench isolation; two-layer planarization process; Circuits; Dielectric films; Etching; Isolation technology; Planarization; Quality control; Random access memory; Resists; Springs; Very large scale integration;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/66.17987

Filename

17987