A 250-MHz-2-GHz wide-range delay-locked loop

Author

Kim, Byung-Guk ; Kim, Lee-Sup

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea

Volume

40

Issue

6

fYear

2005

fDate

6/1/2005 12:00:00 AM

Firstpage

1310

Lastpage

1321

Abstract

This paper describes a wide-range delay-locked loop (DLL) for a synchronous clocking which supports dynamic frequency scaling and dynamic voltage scaling. The DLL has wide operating range by using multiple phases from its delay line. A phase detector (PD) which combines linear and binary characteristics achieves low jitter and fast locking speed. A pulse reshaper makes output pulses of the phase detector have variable pulsewidth and variable voltage level to mitigate the static phase error due to the inherent mismatch of the charge pump. The DLL operates in the range from 250 MHz to 2 GHz. At 1 GHz operating frequency, RMS jitter and peak-to-peak jitter are 1.57 ps and 10.7 ps, respectively.

Keywords

UHF integrated circuits; VHF circuits; delay lock loops; phase detectors; pulse shaping circuits; synchronisation; timing jitter; 250 to 2000 MHz; RMS jitter; clock distribution network; delay line; dynamic frequency scaling; dynamic voltage scaling; multiple phases; peak-to-peak jitter; phase detector; pulse reshaper; static phase error; synchronous clocking; variable pulsewidth level; variable voltage level; wide-range delay-locked loop; Charge pumps; Clocks; Delay lines; Detectors; Digital control; Dynamic voltage scaling; Frequency; Jitter; Phase detection; Phase locked loops; Clock distribution network; delay-locked loop (DLL); jitter; static phase error; synchronous clocking;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2005.848035

Filename

1435609