A low-power SRAM using hierarchical bit line and local sense amplifiers

Author

Yang, Byung-Do ; Kim, Lee-Sup

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea

Volume

40

Issue

6

fYear

2005

fDate

6/1/2005 12:00:00 AM

Firstpage

1366

Lastpage

1376

Abstract

This paper proposes a low power SRAM using hierarchical bit line and local sense amplifiers (HBLSA-SRAM). It reduces both capacitance and write swing voltage of bit lines by using the hierarchical bit line composed of a bit line and sub-bit lines with local sense amplifiers. The HBLSA-SRAM reduces the write power consumption in bit lines without noise margin degradation by applying a low swing signal to the high capacitive bit line and by applying a full swing signal to the low capacitive sub-bit line. The HBLSA-SRAM reduces the swing voltage of bit lines to V_DD/10 for both read and write. It saves 34% of the write power compared to the conventional SRAM. An SRAM chip with 8 K×32 bits is fabricated in a 0.25-μm CMOS process. It consumes 26 mW read power and 28 mW write power at 200 MHz with 2.5 V.

Keywords

CMOS memory circuits; SRAM chips; amplifiers; low-power electronics; 0.25 micron; 2.5 V; 200 MHz; 26 mW; 28 mW; CMOS process; HBLSA-SRAM; full swing signal; hierarchical bit line; high capacitive bit line; local sense amplifiers; low capacitive sub-bit line; low-power SRAM; swing voltage reduction; write power consumption reduction; CMOS process; Capacitance; Degradation; Energy consumption; Low-noise amplifiers; Noise reduction; Pulse amplifiers; Random access memory; SRAM chips; Voltage; Hierarchical bit line; SRAM; local sense amplifier; low power; low swing; write;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2005.848032

Filename

1435615