Generic linear RC delay modeling for digital CMOS circuits

The linear RC delay modeling technique is used to model the timing delays in CMOS circuit empirically. The empirical model, a multidimensional function of various circuit and device parameters, is shown to be simplified to a two-dimensional model which estimates the delay of a CMOS subcircuit in terms of the generic RC delay ad the rise/fall time of the input transition. Accuracy limitations of the linear RC delay model are investigated; namely, (i) the single-time-constant approximation on the multiple-pole network function; (ii) the linear resistance approximation on the nonlinear MOSFET characteristic; and (iii) the step-input waveform assumption. These accuracy problems are handled by: (1) presenting an accuracy measure of the simpler model and an option for using the more accurate two-time-constant model; (2) exploiting the nonlinear body effect in the transmission gate to improve the linear resistance characterization; and (3) using the piecewise-linear characterization on the input rise/fall time effect. The model has been installed in an experimental simulator and tested for various circuits. Comparisons are made with SPICE to validate the model reliability