Optimizing interacting finite state machines using sequential don´t cares

Approaches are presented to multilevel sequential logic synthesis-algorithms and techniques for the area and performance optimizations of interconnected finite state machine descriptions. Techniques are presented for the exploitation of sequential don´t cares in arbitrary, interconnected sequential machine structures. Exploiting these don´t care sequences can results in significant improvements in area and performance. The problem of moving logic across state machine boundaries so as to make particular machines less complex at the possible expense of making others more complex is addressed. Optimization algorithms that incrementally modify state machine structures across latch boundaries are also presented. The use of more global state machine decomposition and factorization algorithms for area optimization is described, and experimental results using these algorithms on sequential circuits are presented