Title :
Background Adaptive Cancellation of Digital Switching Noise in a Pipelined Analog-to-Digital Converter Without Noise Sensors
Author :
Chang, Nick C.-J ; Hurst, Paul J. ; Levy, Bernard C. ; Lewis, Stephen H.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of California, Davis, Davis, CA, USA
Abstract :
Switching noise generated by digital circuits can degrade analog circuit performance in mixed-signal integrated circuits (ICs). In an analog-to-digital converter (ADC), one major source of switching noise is digital output drivers. Traditional methods for mitigating this problem mostly have been to isolate the analog and digital circuits to minimize digital noise coupling into sensitive analog nodes. This paper presents two fully digital and adaptive algorithms, which find and cancel errors due to switching noise coupling at the output of an ADC without using noise sensors. To demonstrate the operation of these algorithms, a 12-bit, 40-MS/s pipelined ADC has been designed and fabricated in 0.18-μm CMOS process. The system consists of an ADC with its own output drivers, and eight other independent digital output drivers (noise buffers) that can be programmed to produce four different kinds of switching noise. The switching noise cancellation (SNC) algorithm estimates noise parameters and stores them in look-up tables. At the ADC output, the effects of switching noise are digitally removed to recover the input samples. Test results show that the ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) of 64.9 dB with all of the noise-generating buffers off. With the noise buffers on, the worst case SNDR before and after SNC is 51.9 dB and 63.7 dB, respectively.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; interference suppression; table lookup; CMOS process; ICs; SNDR; analog circuit performance; background adaptive cancellation; digital circuits; digital noise coupling minimization; digital switching noise cancellation; error cancellation; independent digital output drivers; look-up tables; mixed-signal integrated circuits; noise parameters; noise-generating buffers; pipelined ADC; pipelined analog-to-digital converter; sensitive analog nodes; signal-to-noise-and-distortion-ratio; size 0.18 mum; switching noise coupling; word length 12 bit; Additive noise; Convergence; Couplings; Random access memory; Switches; Switching circuits; Additive noise; analog-to-digital converter; background adaptive noise cancellation; digital switching noise; least-mean-square (LMS) estimation; maximum-likelihood estimation; multiplicative noise; noise-induced gain error; pipelined analog-to-digital converter (ADC); power supply bounce; simultaneous switching noise (SSN); substrate noise;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2014.2314446