DocumentCode :
825071
Title :
Radiation Hardened 64-BIT CMOS/SOS RAM
Author :
Kjar, R.A. ; Peterson, B.E. ; Blandford, J.T.
Author_Institution :
Rockwell International Corporation Anaheim, California 92803
Volume :
23
Issue :
6
fYear :
1976
Firstpage :
1728
Lastpage :
1731
Abstract :
Radiation hardening procedures have been implemented in design, analysis and fabrication of a 64-bit CMOS/SOS RAM. The resultant circuit is a moderately complex (714 transistor), dielectrically isolated integrated circuit which features high performance and high radiation tolerance. Typical electrical parameters include 120 nsec read-access time and 1¿watt/bit standby power dissipation. The SOS construction minimizes radiation-induced transient photocurrents while a hardened gate insulator provides immunity to total dose effects. Transient radiation upset levels exceed 3 × 1010 rads(Si)/sec for short (¿ 50 ns) pulses and ionizing dose hardness exceeds 106 rads(Si). A neutron fluence of 3.65 × 1014 n/cm2 had no effect on circuit operation beyond that expected from the ionizing radiation alone.
Keywords :
CMOS memory circuits; CMOS technology; Circuit testing; Fabrication; Ionizing radiation; Large scale integration; Power dissipation; Power supplies; Radiation hardening; Read-write memory;
fLanguage :
English
Journal_Title :
Nuclear Science, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9499
Type :
jour
DOI :
10.1109/TNS.1976.4328569
Filename :
4328569
Link To Document :
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