DocumentCode
825134
Title
Efficient state reduction methods for PLA-based sequential circuits
Author
Avedillo, M.J. ; Quintana, J.M. ; Huertas, J.L.
Author_Institution
Dept. de Diseno Analogico, Centro Nacional de Microelectronica, CICA, Sevilla, Spain
Volume
139
Issue
6
fYear
1992
fDate
11/1/1992 12:00:00 AM
Firstpage
491
Lastpage
500
Abstract
Experiences with heuristics for the state reduction of finite-state machines are presented and two new heuristic algorithms described in detail. Results on machines from the literature and from the MCNC benchmark set are shown. The area of the PLA implementation of the combinational component and the design time are used as figures of merit. The comparison of such parameters, when the state reduction step is included in the design process and when it is not, suggests that fast state-reduction heuristics should be implemented within FSM automatic synthesis systems.
Keywords
finite state machines; logic arrays; logic design; sequential machines; FSM; PLA implementation; automatic synthesis systems; finite-state machines; state reduction methods;
fLanguage
English
Journal_Title
Computers and Digital Techniques, IEE Proceedings E
Publisher
iet
ISSN
0143-7062
Type
jour
Filename
180007
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