DocumentCode
825481
Title
Area-efficient VLSI architecture for the traceback Viterbi decoder supporting punctured codes
Author
Kim, Sik ; Hwang, Sun-Young
Volume
32
Issue
8
fYear
1996
fDate
4/11/1996 12:00:00 AM
Firstpage
733
Lastpage
735
Abstract
The authors present a novel architecture designed to reduce the storage for decision vectors at the traceback block in the Viterbi decoder. By decreasing the rate of decision vector generation, the data storage requirement has been reduced by 29.9% in the proposed architecture compared to conventional traceback Viterbi decoders. The overall area has been reduced by ~25% when implemented in VLSI
Keywords
VLSI; Viterbi decoding; digital signal processing chips; pipeline processing; VLSI area reduction; area-efficient VLSI architecture; data storage requirement; decision vector generation rate; punctured codes; traceback Viterbi decoder;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19960478
Filename
491059
Link To Document