DocumentCode :
825881
Title :
Low power high-speed CMOS dual-modulus prescaler design with imbalanced phase-switching technique
Author :
Yu, X.P. ; Do, M.A. ; Ma, J.-G. ; Yeo, K.S. ; Wu, R. ; Yan, G.Q.
Author_Institution :
Center for Integrated Circuits & Syst., Nanyang Technol. Univ., Singapore, Singapore
Volume :
152
Issue :
2
fYear :
2005
fDate :
4/8/2005 12:00:00 AM
Firstpage :
127
Lastpage :
132
Abstract :
A novel imbalanced phase-switching technique for high-speed prescaler design is investigated. Different from the traditional 50% duty cycle phase-switching technique, it uses 1/4 duty cycle phases to increase the delay budget in dual-modulus control. It significantly improves the performance of the prescaler in terms of operating frequency and power consumption, compared with the existing 50% duty cycle phase switching technique. This improvement makes it applicable to ultra-high-speed CMOS prescaler design. Two prescalers, with 2-to-1 and 4-to-1 phase switching are designed using this technique. The proposed 2-to-1 phase switching divide-by-7/8 prescaler with simplified topology using the Chartered 0.18 micron CMOS process is capable of operating from 1.5 GHz to 6 GHz with a 7 mW power consumption from a 1.8 V supply. Such operating frequency ranges cover most of the wireless LAN standards. The prescaler with 4-to-1 phase switching can work from 2 GHz to 10 GHz with a power consumption of 15 mW from a 1.8 V supply. The proposed technique is promising in relation to multi-GHz CMOS prescaler design because it eliminates the design trade-offs associated with other techniques.
Keywords :
CMOS logic circuits; frequency dividers; high-speed integrated circuits; low-power electronics; prescalers; 0.18 micron; 1.5 to 6 GHz; 1.8 V; 1/4 duty cycle phases; 15 mW; 2 to 10 GHz; 7 mW; CMOS dual-modulus prescaler design; Chartered 0.18 micron CMOS process; delay budget; frequency divider; high-speed prescaler design; imbalanced phase-switching technique; low power prescaler design; power consumption; ultra-high-speed prescaler design;
fLanguage :
English
Journal_Title :
Circuits, Devices and Systems, IEE Proceedings -
Publisher :
iet
ISSN :
1350-2409
Type :
jour
DOI :
10.1049/ip-cds:20045054
Filename :
1436118
Link To Document :
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