Empirical failure analysis and validation of fault models in CMOS VLSI circuits

Author

Pancholy, Ashish ; Rajski, Ianusz ; Mcnaughton, Mrry J.

Author_Institution

Cypress Semicond. Corp., San Jose, CA, USA

Volume

9

Issue

1

fYear

1992

fDate

3/1/1992 12:00:00 AM

Firstpage

72

Lastpage

83

Abstract

A way to empirically validate fault models and to measure the effectiveness of test sets based on the targeted fault models is described. The authors use automated fault diagnosis of test circuits representative of the circuits being studied and of the fabrication process, cell libraries, and CAD tools used in their development. The design and fabrication of a test chip using an experimental CMOS, 1.5- mu m double-layer metal process are discussed.<>

Keywords

CMOS integrated circuits; VLSI; automatic testing; circuit analysis computing; fault location; integrated circuit testing; 1.5 micron; CAD tools; CMOS VLSI circuits; automated fault diagnosis; cell libraries; double-layer metal process; fabrication process; failure analysis; test chip; test sets; validation of fault models; Automatic testing; Circuit faults; Circuit testing; Design automation; Fabrication; Failure analysis; Fault diagnosis; Libraries; Semiconductor device measurement; Semiconductor device modeling;

fLanguage

English

Journal_Title

Design & Test of Computers, IEEE

Publisher

ieee

ISSN

0740-7475

Type

jour

DOI

10.1109/54.124519

Filename

124519