A novel architecture for queue management in the ATM network

The author presents four architecture designs for queue management in asynchronous transfer mode (ATM) networks and compares their implementation feasibility and hardware complexity. The author introduces the concept of assigning a departure sequence number to every cell in the queue so that the effect of long-burst traffic on other cells is avoided. A novel architecture to implement the queue management is proposed. It applies the concepts of fully distributed and highly parallel processing to schedule the cells´ sending or discarding sequence. To support the architecture, a VLSI chip (called Sequencer), which contains about 150 K CMOS transistors, has been designed in a regular structure such that the queue size and the number of priority levels can grow flexibly