Title :
A 120-mW 3-D rendering engine with 6-Mb embedded DRAM and 3.2-GB/s runtime reconfigurable bus for PDA chip
Author :
Woo, Ramchan ; Yoon, Chi-Weon ; Kook, Jeonghoon ; Lee, Se-Joong ; Yoo, Hoi-Jun
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
fDate :
10/1/2002 12:00:00 AM
Abstract :
A low-power three-dimensional (3-D) rendering engine is implemented as part of a mobile personal digital assistant (PDA) chip. Six-megabit embedded DRAM macros attached to 8-pixel-parallel rendering logic are logically localized with a 3.2-GB/s runtime reconfigurable bus, reducing the area by 25% compared with conventional local frame-buffer architectures. The low power consumption is achieved by polygon-dependent access to the embedded DRAM macros with line-block mapping providing read-modify-write data transaction. The 3-D rendering engine with 2.22-Mpolygons/s drawing speed was fabricated using 0.18-μm CMOS embedded memory logic technology. Its area is 24 mm2 and its power consumption is 120 mW.
Keywords :
CMOS digital integrated circuits; computer graphic equipment; low-power electronics; microprocessor chips; mobile computing; notebook computers; random-access storage; rendering (computer graphics); 0.18 micron; 120 mW; 3.2 GB/s; 3D graphics rendering; 6 Mbit; 8-pixel-parallel rendering logic; CMOS embedded memory logic technology; embedded DRAM macros; line-block mapping; low power consumption; low-power 3D rendering engine; mobile PDA chip; mobile personal digital assistant chip; polygon-dependent access; read-modify-write data transaction; reconfigurable bus; three-dimensional rendering engine; Bandwidth; Clocks; Energy consumption; Engines; Graphics; Personal digital assistants; Random access memory; Reconfigurable logic; Rendering (computer graphics); Runtime;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2002.803051
