A Variation-Tolerant MRAM-Backed-SRAM Cell for a Nonvolatile Dynamically Reconfigurable FPGA

Author

Vatankhahghadim, A. ; Song, W. ; Sheikholeslami, A.

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada

Volume

62

Issue

6

fYear

2015

fDate

Jun-15

Firstpage

573

Lastpage

577

Abstract

Adding a spin-transfer-torque (STT) magnetoresistive random-access memory (MRAM) to a static random-access memory (SRAM) cell to produce an MRAM-backed SRAM cell for a nonvolatile field-programmable gate array (FPGA) is proposed. The proposed cell reduces the time to reconfigure the FPGA following a power-down and enables fast wake-ups and power gating. With the proposed restore operation, data are recalled with no error even in the presence of mismatch. Simulation results confirm that data can be stored in the proposed cell in 80 ns and restored in less than 1 ns.

Keywords

MRAM devices; SRAM chips; field programmable gate arrays; MRAM; SRAM; field programmable gate arrays; magnetoresistive random-access memory; nonvolatile dynamically reconfigurable FPGA; spin-transfer-torque; static random-access memory cell; time 80 ns; Computer architecture; Field programmable gate arrays; Magnetic tunneling; Microprocessors; SRAM cells; Transistors; FPGA; Field-programmable gate arrays (FPGAs); magnetic tunnel junction (MTJ); magnetoresistive random-access memory (MRAM); nonvolatile (NV); spin-transfertorque (STT); spin???transfer???torque (STT); static random-access memory (SRAM);

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2015.2407711

Filename

7051260