SILC dynamics in MOS structures subject to periodic stress

This work investigates stress-induced leakage current (SILC) in thin-oxide MOS capacitors subject to (quasiperiodic) ac voltage stress, under the condition of fixed charge fluence through the oxide. It shows that both trap creation and spontaneous trap annealing play a significant role when the duration of, and the time between, high-voltage pulses are comparable with characteristic times of trap dynamics. A phenomenological model is introduced that is able to accurately represent the main physical phenomena due to pulsed voltage stress under conditions of interest for unconventional programming schemes for fast programming nonvolatile memories (NVMs) with acceptable oxide degradation.