Title :
Floorplan Design for Multimillion Gate FPGAs
Author :
Cheng, Lei ; Wong, Martin D F
Author_Institution :
Dept. of Comput. Sci., Univ. of Illinois at Urbana-Champaign, Urbana, IL
Abstract :
Modern field-programmable gate arrays (FPGAs) have multimillions of gates and future generations of FPGAs will be even more complex. This means that floorplanning tools will soon be extremely important for the physical design of FPGAs. Due to the heterogeneous logic and routing resources of an FPGA, FPGA floorplanning is very different from the traditional floorplanning for application-specific integrated circuits. This paper presents the first FPGA-floorplanning algorithm targeted for FPGAs with heterogeneous resources (e.g., Xilinx´s Spartan3 chips consisting of columns of configurable logic blocks, RAM blocks, and multiplier blocks). This algorithm can generate floorplans for Xilinx´s XC3S5000 architecture (largest of the Spartan3 family) in a few minutes
Keywords :
application specific integrated circuits; circuit layout CAD; field programmable gate arrays; integrated circuit layout; logic CAD; FPGA floorplanning; RAM blocks; Xilinx Spartan3 chips; Xilinx XC3S5000 architecture; application-specific integrated circuits; configurable logic blocks; field-programmable gate arrays; heterogeneous resources; multiplier blocks; Algorithm design and analysis; Application specific integrated circuits; Computer science; Design optimization; Field programmable gate arrays; Integrated circuit technology; Logic circuits; Partitioning algorithms; Read-write memory; Routing; Compaction; field-programmable gate array (FPGA); floorplan; slicing;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2006.882481
