Latency-Guided On-Chip Bus-Network Design

Deep submicrometer technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in critical paths being dominated by global interconnect rather than gate delays. Second, an ultrahigh level of integration mandates design of systems-on-chip that encompass numerous design blocks of decreased functional granularity and increased communication demands. The convergence of these two factors emphasizes the importance of the on-chip bus network as one of the crucial high-performance enablers for future systems-on-chip. An on-chip bus-network design methodology and corresponding set of tools which, for the first time, close the synthesis loop between system and physical design have been developed. The approach has three components: a communication profiler, a bus-network designer, and a fast approximate floorplanner. The communication profiler collects run-time information about the traffic between system cores. The bus-network design component optimizes the bus-network structure by coordinating information from the other two components. The floorplanner aims at creating a feasible floorplan; it also sends feedback about the most constrained parts of the network. The effectiveness of our bus-network design approach on a number of multicore designs is demonstrated