Profile-Driven Instruction Mapping for Dataflow Architectures

Dataflow architectures provide an abundance of computing units that can be statically or dynamically configured to match the computing requirements of the given application. Wire delay has a reduced impact in dataflow architectures because only neighboring architectural entities are allowed to communicate within a single clock cycle. In this paper, the authors propose integer linear programming (ILP)-based placement and routing algorithms for mapping dataflow graphs (DFGs) to dataflow machines. The optimization process is guided by profiling information available from the compiler. The goal is to minimize the total execution time of the given application represented by a DFG under architectural constraints. A hierarchical method to handle the complexity of the initial ILP formulation is proposed. The profile-driven ILP algorithm reduces the total execution time of benchmark applications compared to the conventional wirelength-driven ILP approach. In addition, the ILP-based approach outperforms simulated annealing-based approach