• DocumentCode
    828430
  • Title

    Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip

  • Author

    Rijpkema, E. ; Goossens, K. ; Radulescu, A. ; Dielissen, J. ; van Meerbergen, J. ; Wielage, P. ; Waterlander, E.

  • Volume
    150
  • Issue
    5
  • fYear
    2003
  • Abstract
    Managing the complexity of designing chips containing billions of transistors requires decoupling computation from communication. For the communication, scalable and compositional interconnects, such as networks on chip (NoC), must be used. It is shown that guaranteed services are essential in achieving this decoupling. Guarantees typically come at the cost of lower resource utilisation. To avoid this, they must be used in combination with best-effort services. The key element of this NoC is a router consisting conceptually of two parts; the so-called guaranteed-throughput (GT) and best-effort (BE) routers. The GT and BE router architectures are combined in an efficient implementation by sharing resources. The trade-offs between hardware complexity and efficiency of the combined router are shown that motivate the choices. The reasoning for the trade-offs is validated with a prototype router implementation. A layout is shown of an input-queued wormhole 5×5 router with an aggregate bandwidth of 80 Gbit/s. It occupies 0.26 mm2 in a 0.13 μm technology. This shows that our router provides high performance at reasonable cost, bringing NoCs one step closer
  • Keywords
    circuit CAD <design of router, both guaranteed and best-effort services for nets., chip, trade-offs>; microprocessor chips <design of router, both guaranteed and best-effort services for nets., chip, trade-offs>; 0.13 micron; 80 Gbit/s; BE router architecture; GT router architecture; NoQ; best-effort routers; chip design complexity management; chip networks; compositional interconnects; guaranteed-throughput routers; input-queued wormhole 5×5 router; low resource utilisation; resource sharing; router design; scalable interconnects; transistors;
  • fLanguage
    English
  • Journal_Title
    Computers and Digital Techniques, IEE Proceedings -
  • Publisher
    iet
  • ISSN
    1350-2387
  • Type

    jour

  • DOI
    10.1049/ip-cdt:20030830
  • Filename
    1245598