• DocumentCode
    828445
  • Title

    A new 50-nm nMOSFET with side-gates for virtual source-drain extensions

  • Author

    Choi, Young Jin ; Choi, Byung Yong ; Kim, Kyung Rok ; Lee, Jong Duk ; Park, ByungGook

  • Author_Institution
    Inter-Univ. Semicond. Res. Center (ISRC), Seoul Nat. Univ., South Korea
  • Volume
    49
  • Issue
    10
  • fYear
    2002
  • fDate
    10/1/2002 12:00:00 AM
  • Firstpage
    1833
  • Lastpage
    1835
  • Abstract
    We have proposed and fabricated a novel 50-nm nMOSFET with side-gates, which induce inversion layers for virtual source/drain extensions (SDE). The 50-nm nMOSFETs show excellent suppression of the short channel effect and reasonable current drivability [subthreshold swing of 86 mV/decade, drain-induced barrier lowering (DIBL) of 112 mV, and maximum transconductance (gm) of 470 μS/μm at VD=1.5 V], resulting from the ultra-shallow virtual SDE junction. Since both the main gate and the side-gate give good cut-off characteristics, a possible advantage of this structure in an application to multi-input NAND gates was investigated.
  • Keywords
    MOSFET; inversion layers; logic gates; semiconductor device measurement; 1.5 V; 50 nm; 50-nm nMOSFET; current drivability; cut-off characteristics; drain-induced barrier lowering; inversion layers; maximum transconductance; multi-input NAND gates; short channel effect suppression; side-gates; subthreshold characteristics; subthreshold swing; ultra-shallow virtual SDE junction; virtual source/drain extensions; Bipolar transistors; FETs; Frequency; Gallium arsenide; Heterojunctions; Impedance; MOSFET circuits; Microwave theory and techniques; Microwave transistors; Scattering parameters;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2002.803648
  • Filename
    1036096