Title :
A 0.5-GHz to 2.5-GHz PLL With Fully Differential Supply Regulated Tuning
Author :
Brownlee, Merrick ; Hanumolu, Pavan Kumar ; Mayaram, Kartikeya ; Moon, Un-Ku
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR
Abstract :
This paper describes a wide-range clock generation phase-locked loop (PLL) incorporating several features that make it suitable for integration in highly scaled processes. A fully differential supply regulated tuning scheme is used to combat power supply noise. The charge pump uses a resistor rather than an active current source to define the pumping current in order to reduce the charge pump flicker noise. Fabricated in a 0.18-mum CMOS process, the PLL occupies 0.15 mm2 die area and achieves a frequency range of 0.5 to 2.5 GHz. When operating at 2.4 GHz, the power consumption is 14 mA from a 1.8-V supply while the jitter is 2.36 ps rms
Keywords :
CMOS integrated circuits; UHF integrated circuits; circuit tuning; flicker noise; integrated circuit noise; phase locked loops; power supply circuits; voltage multipliers; voltage-controlled oscillators; 0.18 micron; 0.5 to 2.5 GHz; 1.8 V; 14 mA; 2.36 ps; CMOS process; charge pump; flicker noise; fully differential supply regulated tuning; power supply noise; pumping current; voltage-controlled oscillator; wide-range clock generation phase-locked loop; 1f noise; CMOS process; Charge pumps; Clocks; Energy consumption; Frequency; Jitter; Phase locked loops; Power supplies; Resistors; Phase-locked loop; charge pump; flicker noise; power supply noise; supply regulation; voltage-controlled oscillator;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2006.884194
