Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies

Author

Fiorenza, John K. ; Sepke, Todd ; Holloway, Peter ; Sodini, Charles G. ; Lee, Hae-Seung

Author_Institution

MIT, Cambridge, MA

Volume

41

Issue

12

fYear

2006

Firstpage

2658

Lastpage

2668

Abstract

A comparator-based switched-capacitor circuit (CBSC) technique is presented for the design of analog and mixed-signal circuits in scaled CMOS technologies. The technique involves replacing the operational amplifier in a standard switched-capacitor circuit with a comparator and a current source. During charge transfer, the comparator detects the virtual ground condition in place of the opamp which normally forces the virtual ground condition. A prototype 1.5-bit/stage 10-bit 7.9-MS/s pipeline ADC was designed using the comparator-based switched-capacitor technique. The prototype ADC was implemented in 0.18-mum CMOS. It achieves an ENOB of 8.6 bits for a 3.8-MHz input signal and dissipates 2.5 mW

Keywords

CMOS integrated circuits; analogue-digital conversion; comparators (circuits); mixed analogue-digital integrated circuits; switched capacitor networks; 0.18 micron; 10 bit; 2.5 mW; 3.8 MHz; analog circuit; analog-to-digital conversion; charge transfer; comparator circuit; current source; mixed-signal circuits; pipeline ADC; scaled CMOS technologies; switched-capacitor circuits; virtual ground condition; Analog circuits; CMOS analog integrated circuits; CMOS technology; Charge transfer; Energy consumption; Operational amplifiers; Pipelines; Prototypes; Switched capacitor circuits; Switching circuits; A/D; ADC; CBSC; analog-to-digital conversion; comparator-based switched-capacitor circuits; pipeline; scaled CMOS; switched-capacitor circuits;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2006.884330

Filename

4014611