Title :
A 1.9-GHz Single-Chip CMOS PHS Cellphone
Author :
Si, William W. ; Mehta, Srenik ; Samavati, Hirad ; Terrovitis, Manolis ; Mack, Michael ; Onodera, Keith ; Jen, Steve ; Luschas, Susan ; Hwang, Justin ; Mendis, Suni ; Su, David ; Wooley, Bruce
Author_Institution :
Atheros Commun., Santa Clara, CA
Abstract :
A single-chip CMOS PHS cellphone, integrated in a 0.18-mum CMOS technology, implements all handset functions including radio, voice, audio, MODEM, TDMA controller, CPU, and digital interfaces. Both the receiver and transmitter are based on a direct conversion architecture. The RF transceiver achieves -106 dBm receive sensitivity and +4 dBm EVM-compliant transmit power. The local oscillator, based on a sigma-delta fractional-N synthesizer, has a phase noise of -118 dBc/Hz at 600kHz offset and settling time of 15 mus. The current consumption for the receiver, transmitter and synthesizer are 32 mA, 29 mA, and 25 mA, respectively, from a 3.0 V supply
Keywords :
CMOS integrated circuits; UHF integrated circuits; frequency synthesizers; oscillators; personal communication networks; phase locked loops; phase noise; transceivers; 0.18 micron; 1.9 GHz; 25 mA; 29 mA; 3 V; 32 mA; CMOS technology; RF transceiver; digital interfaces; direct conversion architecture; fast settling synthesizer; frequency synthesizer; handset functions; local oscillator; personal handy-phone; phase noise; phase-locked loop; receiver; sigma-delta fractional-TV synthesizer; single-chip CMOS PHS cellphone; transmitter; CMOS technology; Cellular phones; Digital control; Modems; Radio control; Radio transmitters; Receivers; Synthesizers; Telephone sets; Time division multiple access; CMOS integrated circuits; RF transceiver; direct conversion; fast settling synthesizer; fractional-N synthesizer; frequency synthesizer; personal handy-phone (PHS); phase noise; phase-locked loop (PLL); transceiver;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2006.884790
