A Memory-Based Logic Block With Optimized-for-Read SRAM for Energy-Efficient Reconfigurable Computing Fabric

Author

Yueh, Wen ; Chatterjee, Subho ; Zia, Muneeb ; Bhunia, Swarup ; Mukhopadhyay, Saibal

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

Volume

62

Issue

6

fYear

2015

fDate

Jun-15

Firstpage

593

Lastpage

597

Abstract

A memory-based logic block (MLB), which is a building block for memory-based reconfigurable computing framework, is presented in 130-nm CMOS. The MLB is designed with an optimized-for-read (OFR) 6T static random access memory (SRAM)-based lookup table and demonstrates single- and multicycle evaluation of complex functions. Power-aware mapping leverages the data-dependent read power of the OFR SRAM to reduce MLB evaluation power.

Keywords

SRAM chips; reconfigurable architectures; table lookup; CMOS; MLB evaluation power; OFR SRAM; complex functions; energy-efficient reconfigurable computing fabric; lookup table; memory-based logic block; memory-based reconfigurable computing framework; multicycle evaluation; optimized-for-read SRAM; power aware mapping leverages; static random access memory; Current measurement; Field programmable gate arrays; Power measurement; SRAM cells; Table lookup; Memory-based computing; Static Random Access Memory; memory based computing; reconfigurable hardware; static random access memory (SRAM);

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2015.2407792

Filename

7051284