DocumentCode :
830258
Title :
Three generations of asynchronous microprocessors
Author :
Martin, Alain J. ; Nyström, Mika ; Wong, Catherine G.
Author_Institution :
California Inst. of Technol., Pasadena, CA, USA
Volume :
20
Issue :
6
fYear :
2003
Firstpage :
9
Lastpage :
17
Abstract :
We trace the evolution of Caltech asynchronous processors from a simple proof of concept, to a high-performance MIPS-like processor using a different buffer circuit for better performance, to the latest 8051 clone targeting low-energy operation. We describe the control aspects of the evolving circuit styles. We describe these three generations of asynchronous microprocessors (Caltech asynchronous processors, MiniMIPS and Lutonium) and the corresponding circuit families and design methods. The asynchronous circuits we use are called quasidelay-insensitive (QDI) circuits. A QDI circuit involves no assumption about, or knowledge of, delays in operators and wires, except for isochronic forks, which the designer assumes have similar delays on the different branches. QDI circuits are the most conservative asynchronous circuits in terms of delays.
Keywords :
VLSI; asynchronous circuits; buffer circuits; circuit complexity; integrated circuit design; microprocessor chips; Caltech asynchronous processors; Lutonium microcontroller; MlPS-like processor; VLSI; asynchronous microprocessors; buffer circuit; circuit complexity; circuit design methods; quasidelay-insensitive circuits; Asynchronous circuits; Cogeneration; Delay; Design methodology; Microprocessors; Production; Robustness; Throughput; Voltage; Wires;
fLanguage :
English
Journal_Title :
Design & Test of Computers, IEEE
Publisher :
ieee
ISSN :
0740-7475
Type :
jour
DOI :
10.1109/MDT.2003.1246159
Filename :
1246159
Link To Document :
بازگشت