DocumentCode
830554
Title
A false-lock-free clock/data recovery PLL for NRZ data using adaptive phase frequency detector
Author
Idei, Gijun ; Kunieda, Hiroaki
Author_Institution
Dept. of Commun. & Integrated Syst., Tokyo Inst. of Technol., Japan
Volume
50
Issue
11
fYear
2003
Firstpage
896
Lastpage
900
Abstract
An adaptive four-state phase-frequency detector (PFD) for clock and data recovery (CDR) phased-lock loop (PLL) of nonreturn to zero (NRZ) data is presented. The PLL achieves false-lock free operation with rapid frequency capture and wide capture range. The false-lock-free nature of the PLL is achieved by adaptively adjusting data delay in the proposed PFD. Circuitry and corresponding operation of blocks in the PFD and overall PLL architecture that enables rapid frequency capture and prevents false lock are described in detail.
Keywords
CMOS analogue integrated circuits; phase detectors; phase locked loops; synchronisation; timing jitter; voltage-controlled oscillators; CMOS LSI; adaptive four-state phase-frequency detector; clock and data recovery PLL; current-control oscillator; false-lock free operation; nonreturn to zero data; rapid frequency capture; timeslot control; voltage-control oscillator; wide capture range; Bit rate; Circuits; Clocks; Delay; Jitter; Optical signal processing; Phase detection; Phase frequency detector; Phase locked loops; Voltage-controlled oscillators;
fLanguage
English
Journal_Title
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
Publisher
ieee
ISSN
1057-7130
Type
jour
DOI
10.1109/TCSII.2003.819115
Filename
1246368
Link To Document