Design strategies of cascaded CML gates

Author

Alioto, Massimo ; Palumbo, Gaetano

Author_Institution

DII, Univ. of Siena, Italy

Volume

53

Issue

2

fYear

2006

Firstpage

85

Lastpage

89

Abstract

In this paper, a strategy to design paths consisting of cascaded bipolar current-mode logic gates is proposed. In particular, explicit design criteria are derived both for low-power non-critical paths and high-speed critical paths. The analytical results are simple to be applied to actual circuits avoiding the usual time-consuming approach based on iterative simulations with a trial-and-error procedure. Moreover, it provides the designer with a deeper understanding of the power-delay trade-off. Design examples based on a 20-GHz bipolar process are introduced to validate the procedure and clarify its application.

Keywords

bipolar logic circuits; current-mode logic; logic design; logic gates; 20 GHz; bipolar current-mode logic gates; cascaded CML gates; design methodology; digital integrated circuits; high-speed integrated circuits; integrated circuit design; Analytical models; Circuit simulation; Delay; Design optimization; Digital integrated circuits; Energy consumption; Energy management; Logic circuits; Logic design; Logic gates; Bipolar digital integrated circuits; current mode logic (CML); design methodology; digital circuits; digital integrated circuits; high-speed integrated circuits; integrated circuit design;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2005.856672

Filename

1593961