Title :
A low-power CMOS analog multiplier
Author :
Chen, Chunhong ; Li, Zheng
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Windsor, Ont., Canada
Abstract :
A multiplier is an important component for many analog applications. This paper presents a low power CMOS analog multiplier with performance analysis and design considerations. Experiments with SPICE simulation and results from chip testing show that this new structure has extremely low power consumption with comparable linearity and noise performance, making it very attractive for use in a variety of analog circuits.
Keywords :
CMOS analogue integrated circuits; analogue multipliers; low-power electronics; SPICE simulation; analog integrated circuits; chip testing; low power consumption; low-power CMOS analog multiplier; low-power design; CMOS analog integrated circuits; CMOS technology; Circuit simulation; Circuit testing; Energy consumption; Linearity; MOSFETs; Performance analysis; SPICE; Voltage; Analog integrated circuits; CMOS; analog multipliers; low-power design;
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2005.857089
