• DocumentCode
    830601
  • Title

    A low-power CMOS analog multiplier

  • Author

    Chen, Chunhong ; Li, Zheng

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Windsor, Ont., Canada
  • Volume
    53
  • Issue
    2
  • fYear
    2006
  • Firstpage
    100
  • Lastpage
    104
  • Abstract
    A multiplier is an important component for many analog applications. This paper presents a low power CMOS analog multiplier with performance analysis and design considerations. Experiments with SPICE simulation and results from chip testing show that this new structure has extremely low power consumption with comparable linearity and noise performance, making it very attractive for use in a variety of analog circuits.
  • Keywords
    CMOS analogue integrated circuits; analogue multipliers; low-power electronics; SPICE simulation; analog integrated circuits; chip testing; low power consumption; low-power CMOS analog multiplier; low-power design; CMOS analog integrated circuits; CMOS technology; Circuit simulation; Circuit testing; Energy consumption; Linearity; MOSFETs; Performance analysis; SPICE; Voltage; Analog integrated circuits; CMOS; analog multipliers; low-power design;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems II: Express Briefs, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1549-7747
  • Type

    jour

  • DOI
    10.1109/TCSII.2005.857089
  • Filename
    1593964
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=830601