Jittery Signal Generation for High-Speed Interconnect Simulation

By generating clock and data waveforms in the frequency domain through a truncated Fourier series, absolute control over both voltage noise and symbol transition timing is achieved. A parameterized Fourier series signal model is derived and used to form clock and data waveforms exhibiting arbitrary noise and jitter characteristics. The method not only facilitates more accurate interconnect modeling in tools like Matlab and Simulink, but also provides a simple means for generating realistic signals that may be imported into Spice-based simulators.