• DocumentCode
    830846
  • Title

    A Scalable Digitalized Buffer for Gigabit I/O

  • Author

    Lu, Hungwen ; Su, Chauchin ; Liu, Chien-Nan

  • Author_Institution
    Electr. Eng. Dept., Nat. Central Univ., Jungli
  • Volume
    55
  • Issue
    10
  • fYear
    2008
  • Firstpage
    1026
  • Lastpage
    1030
  • Abstract
    A serial input-output (I/O) composed of inverters and transmission gates only is proposed to achieve high supply voltage scalability and low area overhead. The inverter with an inductive biasing circuit can extend bandwidth, and reduce the simultaneous switching noise simultaneously. With a TSMC 0.18-mum CMOS process, the I/O occupies an area of 0.014 mm2 and operates from 4 Gbps@1.9 V to 1.5 Gbps@1.1 V.
  • Keywords
    CMOS integrated circuits; buffer circuits; driver circuits; TSMC CMOS process; high-supply voltage scalability; inductive biasing circuit; inverters; scalable digitalized buffer; serial gigabit input-output; simultaneous switching noise; size 0.18 mum; transmission gates; voltage 1.9 V to 1.1 V; Buffer; input–output (I/O); simultaneous switching noise (SSN);
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems II: Express Briefs, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1549-7747
  • Type

    jour

  • DOI
    10.1109/TCSII.2008.925661
  • Filename
    4595702
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=830846