Variable ordering algorithms for ordered binary decision diagrams and their evaluation

Author

Fujita, Masahiro ; Fujisawa, Hisanori ; Matsunaga, Yusuke

Author_Institution

Fujitsu Lab. Ltd., Kawasaki, Japan

Volume

12

Issue

1

fYear

1993

fDate

1/1/1993 12:00:00 AM

Firstpage

6

Lastpage

12

Abstract

Ordered binary decision diagrams (OBDDs) use restricted decision trees with shared subgraphs. The ordering of variables is fixed throughout an OBDD diagram. However, the size of an OBDD is very sensitive to variable ordering, especially for large circuits. The results of experiments in variable ordering using an experimentally practical algorithm are presented. The algorithm is basically a depth-first traversal through a circuit from the output to the inputs. With this algorithm, circuits having more than 3000 gates and more than 100 inputs can be expressed in reasonable CPU time and with practical memory requirements

Keywords

circuit CAD; diagrams; logic CAD; trees (mathematics); CAD; ordered binary decision diagrams; restricted decision trees; shared subgraphs; variable ordering algorithms; Boolean functions; Central Processing Unit; Circuits; Data structures; Decision trees; Design optimization; Digital systems; Input variables; Logic; Minimization methods;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.184839

Filename

184839