DocumentCode :
832046
Title :
Multiple fault testing using minimal single fault test set for fanout-free circuits
Author :
Jone, Wen-Ben ; Madden, Patrick H.
Author_Institution :
Dept. of Comput. Sci., New Mexico Inst. of Min. & Technol., Socorro, NM, USA
Volume :
12
Issue :
1
fYear :
1993
fDate :
1/1/1993 12:00:00 AM
Firstpage :
149
Lastpage :
157
Abstract :
The authors examine the properties of fanout-free circuits, and develop an algorithm to generate single stuck-at fault test experiments that also detect all multiple stuck-at faults. These experiments are shown to be minimal in size. Results demonstrate that elaborate selection of nonsensitizing test pattern guarantees the detection of all multiple stuck-at faults using single stuck-at test experiments. The algorithm is deterministic, and will produce test sets for tree circuits containing any mixture of AND, OR, NOT, NAND, and NOR gates. The results can be extensively applied to multiple stuck-at fault detection for pseudo tree circuits such as parity checkers. The time complexity of the algorithm is determined to the O(n2), where n is the number of gates in the circuit
Keywords :
VLSI; fault location; integrated circuit testing; integrated logic circuits; logic testing; AND gates; NAND gates; NOR gates; NOT gates; OR gates; VLSI logic circuits; fanout-free circuits; minimal single fault test set; multiple fault testing; multiple stuck-at faults; parity checkers; pseudo tree circuits; single stuck-at fault test; time complexity; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Computer science; Electrical fault detection; Fault detection; Laboratories; Test pattern generators; Very large scale integration;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.184851
Filename :
184851
Link To Document :
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