• DocumentCode
    832846
  • Title

    Technique for 1-dimensional VLSI layout generation

  • Author

    Singh, U. ; Chen, C.-Y.R.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
  • Volume
    139
  • Issue
    6
  • fYear
    1992
  • fDate
    12/1/1992 12:00:00 AM
  • Firstpage
    635
  • Lastpage
    645
  • Abstract
    The layout and synthesis system RESCUE presented by Shaw et al. (1986) is briefly reviewed. It is a system for implementing random logic using an array layout style. RTL equations are realised by a horizontal row of cells which may contain both static and dynamic circuits. Signals are carried by polysilicon lines in horizontal rows. Algorithmic improvements are suggested in three areas. First, the mincut algorithm is proposed for the cell-assignment problem. Secondly, a new algorithm is presented which determines a placement for the polysilicon lines in a way that allows narrower cells to be designed. Another algorithm based on a technique developed by the authors is proposed for designing cells so as to optimise their areas. The complexity of the final set of algorithms is O(E log E) where E is the number of RTL equations. Improvements range from 5.5% to 50%
  • Keywords
    VLSI; circuit layout CAD; computational complexity; integrated circuit technology; logic CAD; logic arrays; 1D IC layout; RESCUE; RTL equations; Si; VLSI layout generation; array layout style; cell-assignment problem; complexity; dynamic circuits; mincut algorithm; polysilicon lines placement; random logic; static circuits; synthesis system;
  • fLanguage
    English
  • Journal_Title
    Circuits, Devices and Systems, IEE Proceedings G
  • Publisher
    iet
  • ISSN
    0956-3768
  • Type

    jour

  • Filename
    185014