An integrated CMOS PLL for low-jitter applications

Author

Herzel, Frank ; Fischer, Gunter ; Gustat, Hans ; Weger, Peter

Author_Institution

IHP, Frankfurt, Germany

Volume

49

Issue

6

fYear

2002

fDate

6/1/2002 12:00:00 AM

Firstpage

427

Lastpage

429

Abstract

This brief presents a fully integrated integer-N frequency synthesizer with a frequency-tuning range from 2.4 to 2.9 GHz and root-mean-square (rms) jitter below 2.5 ps over 350 MHz. The employed architecture using an inductance-capacitance (L-C) oscillator with two control inputs combines a wide tuning range with a low noise sensitivity. Potential applications include clock generation in microprocessors and clock recovery in fiberoptic receivers.

Keywords

CMOS digital integrated circuits; circuit tuning; digital phase locked loops; frequency synthesizers; synchronisation; timing jitter; 2.4 to 2.9 GHz; 350 MHz; RMS jitter; clock generation; clock recovery; frequency-tuning range; inductance-capacitance oscillator; integer-N frequency synthesizer; integrated CMOS PLL; low-jitter applications; noise sensitivity; Circuit optimization; Clocks; Frequency synthesizers; Jitter; Microprocessors; Phase locked loops; Phase noise; Tuning; Voltage-controlled oscillators; Working environment noise;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/TCSII.2002.802965

Filename

1038829