• DocumentCode
    83377
  • Title

    Sub-threshold SRAM bit cell pnn for VDDmin and power reduction

  • Author

    Chien, Y.C. ; Chiang, I.H. ; Wang, J.S.

  • Author_Institution
    SoC/AIM-HI Center & Dept. of EE, Nat. Chung Cheng Univ., Chiayi, Taiwan
  • Volume
    50
  • Issue
    20
  • fYear
    2014
  • fDate
    September 25 2014
  • Firstpage
    1427
  • Lastpage
    1429
  • Abstract
    The bit cell is a key component that determines the VDDmin and power consumption of a sub-threshold static random access memory (SRAM). A new bit cell with a pnn-type latch structure is proposed. The analysis and measurement results indicate that the pnn bit cell outperforms the conventional bit cells in terms of VDDmin and power reduction.
  • Keywords
    SRAM chips; flip-flops; power consumption; PNN- type latch structure; VDDmin; bit cell; power reduction; sub-threshold SRAM;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el.2014.2357
  • Filename
    6908630
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=83377