A 10-bit 5-Msample/s CMOS two-step flash ADC

Author

Doernberg, Joey ; Gray, Paul R. ; Hodges, David A.

Volume

24

Issue

2

fYear

1989

fDate

4/1/1989 12:00:00 AM

Firstpage

241

Lastpage

249

Abstract

A 10-b, 5Msample/s, two-step flash A/D converter fabricated in a 1.6 mu m CMOS process is described. The architecture is based on a resistor string and capacitor arrays and was developed to overcome the disadvantages of the previous approaches, namely flash, pipelined, and classical two-step converters. With minimal capacitor matching requirements and comparator offset voltage cancellation, the converter is monotonic. To minimize charge-injection errors the converter is fully differential. A high-speed comparator architecture using three comparator stages was designed to provide a gain of more than 1000, and a comparison time of less than 10 ns. The total area of the converter excluding the bonding pads is 54 kmil/sup 2/. Power dissipation is 350 mW, of which 60 mW is dissipated in the resistor string.<>

Keywords

CMOS integrated circuits; analogue-digital conversion; 1.6 micron; 350 mW; 5 MHz; CMOS; capacitor arrays; charge-injection errors; chip architecture; comparator offset voltage cancellation; comparison time; fully differential; gain; high-speed comparator architecture; minimal capacitor matching requirements; monotonic; resistor string; three comparator stages; total area; two-step flash ADC; Capacitors; Circuits; Diodes; Feedback; Laboratories; MOSFETs; Operational amplifiers; Resistors; Signal resolution; Timing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.18582

Filename

18582