The architectures and design of a 20-MHz real-time DSP chip set

Author

Ruetz, Peter A.

Author_Institution

LSI Logic Corp., Menlo Park, CA, USA

Volume

24

Issue

2

fYear

1989

fDate

4/1/1989 12:00:00 AM

Firstpage

338

Lastpage

348

Abstract

A set of four real-time 20-MHz digital signal processor (DSP) chips has been designed, fabricated, and tested. The chips include a 64-tap programmable FIR (finite impulse response) filter, a 1024-tap binary filter and template matcher, a 64-tap rank-value filter, and an eight-line 512-pixel video line delay. The circuits were implemented in a 1.5-μm CMOS process and are fully functional with a 20-MHz clock rate. The processors have reconfigurable windows to allow processing on both one-dimensional and two-dimensional data. The FIR filters can be used in multiprocessor systems to increase the window size and the data precision

Keywords

CMOS integrated circuits; digital filters; digital signal processing chips; 1.5 micron; 20 MHz; CMOS; FIR filters; binary filter; clock rate; data precision; digital signal processor; four chip set; multiprocessor systems; one dimensional data; programmable FIR filters; rank-value filter; real-time DSP chip set; reconfigurable windows; template matcher; two-dimensional data; video line delay; window size; CMOS process; Circuit testing; Clocks; Delay lines; Digital signal processing chips; Digital signal processors; Finite impulse response filter; Matched filters; Multiprocessing systems; Signal design;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.18594

Filename

18594