• DocumentCode
    834363
  • Title

    Node duplication and routing algorithms for quantum-dot cellular automata circuits

  • Author

    Chung, W.J. ; Smith, B. ; Lim, S.K.

  • Author_Institution
    Dept. of Electr. Eng., Stanford Univ., CA
  • Volume
    153
  • Issue
    5
  • fYear
    2006
  • fDate
    10/1/2006 12:00:00 AM
  • Firstpage
    497
  • Lastpage
    505
  • Abstract
    Quantum-dot cellular automata (QCA) is a novel computing mechanism that can represent binary information based on the spatial distribution of electron charge configuration in chemical molecules. QCA circuit layout is currently restricted to a single layer with very limited number of wire crossings permitted. Thus, wire crossing minimisation is crucial in improving the manufacturability of QCA circuits. We present the first QCA node duplication and routing algorithms for wire crossing minimisation. Our duplication algorithm named fan-out tolerance duplication (FTD) explores node duplication in conjunction with node placement using K-layered bipartite graphs (KLBG). FTD successfully removes additional crossings at the cost of increased area and allows flexible tradeoff between area and wire crossing. Our routing algorithm, namely cycle breaker (CB), constructs a modified vertical constraint graph (VCG) to enforce additional vertical relation for wire crossing reduction. We formulate and provide a heuristic solution for the weighted minimum feedback edge set problem to effectively remove cycles from the VCG. As a result, FTD and CB achieve wire crossing results that are very close to theoretical lower bound and outperform the conventional algorithms significantly
  • Keywords
    cellular automata; circuit layout; graph theory; logic design; network routing; quantum computing; quantum dots; K-layered bipartite graphs; QCA circuit layout; QCA circuit manufacturability; binary information; chemical molecules; cycle breaker; electron charge configuration; fan-out tolerance duplication; node duplication; quantum-dot cellular automata circuits; routing algorithms; spatial distribution; vertical constraint graph; wire crossing minimisation;
  • fLanguage
    English
  • Journal_Title
    Circuits, Devices and Systems, IEE Proceedings -
  • Publisher
    iet
  • ISSN
    1350-2409
  • Type

    jour

  • DOI
    10.1049/ip-cds:20050278
  • Filename
    4015860