DocumentCode
834406
Title
Trench isolation step-induced (TRISI) narrow width effect on MOSFET
Author
Kim, Youngmin ; Sridhar, Seetharaman ; Chatterjee, Amitava
Author_Institution
Silicon Technol. Dev., Texas Instrum. Inc., Dallas, TX, USA
Volume
23
Issue
10
fYear
2002
Firstpage
600
Lastpage
602
Abstract
We report a new narrow-width effect that manifests as an increase in threshold voltage V/sub th/ and in its standard deviation /spl sigma//sub Vth/ as the width W of a MOSFET is reduced to be comparable to the trench isolation step height and the gate polysilicon thickness. At such small W the conformal deposition of polysilicon across the step between the active and isolation regions induces the polysilicon gate to be thicker over the active region. This increased thickness is shown to increase the poly depletion effect causing V/sub th/ shift, a higher /spl sigma//sub Vth/, and higher Vth mismatch. Thus, attention to this detrimental trench isolation step-induced (TRISI) narrow width effect is essential for scaled isolation design.
Keywords
CMOS integrated circuits; MOSFET; chemical mechanical polishing; conformal coatings; isolation technology; CMOS process; MOSFET; active region; chemical mechanical planarization process; gate polysilicon thickness; poly depletion effect; polysilicon conformal deposition; polysilicon gate; scaled isolation design; shallow trench isolation; standard deviation; threshold voltage; threshold voltage mismatch; trench isolation step height; trench isolation step-induced narrow width effect; Boron; Implants; Instruments; Isolation technology; MOSFET circuits; Oxidation; Silicon; Stress; Surfaces; Threshold voltage;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/LED.2002.802589
Filename
1039180
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