An experimental 2-bit/cell storage DRAM for macrocell or memory-on-logic application

Author

Furuyama, Tohru ; Ohsawa, Takashi ; Nagahama, Yousei ; Tanaka, Hiroto ; Watanabe, Yohji ; Kimura, Tohru ; Muraoka, Kazuyoshi ; Natori, Kenji

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

24

Issue

2

fYear

1989

fDate

4/1/1989 12:00:00 AM

Firstpage

388

Lastpage

393

Abstract

A multiple-level 2-bit/cell storage technique for DRAMs (dynamic random-access memories) has been developed. The total RAM area is reduced and the cell array is cut in half. Since the memory cell area is especially defect-sensitive, this technique is highly effective for process yield improvement. Reasonable access time has been realized with this technique: 170 ns is still fast enough for many ASIC (application-specific integrated circuit) memory applications. This technique meets the requirement of high density and moderate speed. It was found that the 2-bit/cell storage technique is suitable for macrocell or memory-on-logic type application.<>

Keywords

CMOS integrated circuits; integrated memory circuits; random-access storage; 170 ns; 2-bit/cell storage DRAM; ASIC; CMOS; DRAMs; RAM area reduction; access time; cell array; dynamic random-access memories; experimental RAM; high density; macrocell; memory-on-logic application; moderate speed; multiple-level 2-bit/cell storage technique; process yield improvement; Application specific integrated circuits; Capacitors; Fabrication; Logic; Macrocell networks; Microcomputers; Potential well; Random access memory; Read-write memory; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.18599

Filename

18599