Title :
Junction temperature induced thermal snapback breakdown of MOSFET device
Author_Institution :
SMARTMOS Technol. Center, Motorola, Tempe, AZ, USA
Abstract :
Continued scaling of semiconductor devices is increasingly concerned with physical limits of maximum junction temperature. This paper reports the mechanism of a junction temperature induced thermal snapback breakdown of a MOSFET device in the absence of the high electric field. The thermal snapback breakdown results from Fermi-level shift and thermally generated hole current driven by the junction temperature. It occurs before the junction temperature reaches the intrinsic level and thus determines a fundamental physical limit of MOSFET device operation.
Keywords :
Fermi level; MOSFET; avalanche breakdown; semiconductor device breakdown; semiconductor device models; temperature distribution; BiCMOS technology; Fermi-level shift; MOSFET; avalanche snapback breakdown; intrinsic level; junction temperature induced thermal snapback breakdown; lateral-diffused MOS transistors; maximum junction temperature; physical limits; power density limit; semiconductor device scaling; thermally generated hole current; Density measurement; Electric breakdown; Electrothermal effects; Isothermal processes; MOSFET circuits; Power measurement; Pulse measurements; Semiconductor device breakdown; Semiconductor devices; Temperature;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2002.803762
