A simple technology for superjunction device fabrication: polyflanked VDMOSFET

Author

Gan, Kian Paau ; Yang, Xin ; Liang, Yung C. ; Samudra, Ganesh S. ; Yong, Liu

Author_Institution

Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore

Volume

23

Issue

10

fYear

2002

Firstpage

627

Lastpage

629

Abstract

The charge compensation based novel superjunction (SJ) MOSFET outperforms its conventional counterparts. However, the production of SJ devices is limited by a complicated and costly fabrication process. In this letter, a feasible technology for polyflanked vertical double-diffused MOS SJ structure, as in Gan et al. (2001), is introduced and demonstrated to have greatly reduced fabrication costs, simplified processes, and overcome the interdiffusion problem of SJ columns. This brings forth the new milestone that SJ MOS devices can now be fabricated by standard cleanroom facilities.

Keywords

chemical interdiffusion; power MOSFET; semiconductor device breakdown; semiconductor technology; device breakdown; fabrication process; feasible technology; interdiffusion problem; oxide-bypassed termination; partial mask layout; polyflanked VDMOSFET; polyflanked vertical double-diffused superjunction MOSFET; power MOSFET; Breakdown voltage; Costs; Doping; Fabrication; Gallium nitride; MOS devices; MOSFET circuits; Power MOSFET; Production; Silicon;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2002.803770

Filename

1039189