Title :
A systolic VSLI chip for implementing orthogonal transforms
Author :
Burleson, Wayne P. ; Scharf, Louis L. ; Gabriel, Arthur R. ; Endsley, Neil H.
Author_Institution :
Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
fDate :
4/1/1989 12:00:00 AM
Abstract :
The design of a systolic VLSI chip is described for the implementing of signal processing algorithms that may be decomposed into a product of simple real rotations. These include orthogonal transformations. Applications of this chip include projections, discrete Fourier and cosine transforms, and geometrical transformations. Large transforms may be computed by ´tilting´ together many chips for increased throughput. A CMOS VLSI chip containing 138000 transistors in a 5*3 array of rotators has been designed, fabricated, and tested. The chip has a 32-MHz clock and performs real rotations at a rate of 30 MHz. The systolic nature of the chip makes use of a fully synchronous bit-serial interconnect and a very regular structure at the rotator and bit levels. A distributed arithmetic scheme is used to implement the matrix-vector multiplication of the rotation.<>
Keywords :
CMOS integrated circuits; VLSI; cellular arrays; computerised signal processing; digital arithmetic; digital signal processing chips; parallel architectures; pipeline processing; real-time systems; transforms; 30 MHz; 32 MHz; CMOS; DSP chip; cosine transforms; discrete Fourier transforms; distributed arithmetic scheme; geometrical transformations; matrix-vector multiplication; orthogonal transforms; parallel processing; pipeline computation; projections; real rotations; real-time processing; signal processing algorithms; synchronous bit-serial interconnect; systolic VSLI chip; Algorithm design and analysis; Clocks; Discrete Fourier transforms; Discrete transforms; Fourier transforms; Signal design; Signal processing algorithms; Testing; Throughput; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
