A 250-Mbit/s CMOS crosspoint switch

Voltage swing reduction and constant current steering techniques for high-speed CMOS crosspoint switches are described. These techniques reduced crosstalk and intersymbol interference originating from capacitive and inductive couplings along the high-speed channels. An experimental 16*16 crosspoint switch using the techniques has achieved a worst-case data rate of 250 Mbit/s with 80% eye opening and 0.2-ns timing jitter from a 5-V supply. The worst crosstalk noise is 140 mV/sub p-p/, average delay through the switch is 6 ns, and power consumption is 900 mW. Also, the scaling experiment has demonstrated robustness of the design against blind scaling.<>