Title :
Advanced design approaches for SFQ logic circuits based on the binary decision diagram
Author :
Nishigai, T. ; Ito, M. ; Yoshikawa, N. ; Obata, K. ; Takagai, K. ; Takagai, N. ; Fujimaki, A. ; Terai, H. ; Yorozu, S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Yokohama Nat. Univ., Japan
fDate :
6/1/2005 12:00:00 AM
Abstract :
We have been investigating a design methodology of SFQ logic circuits based on the binary decision diagram (BDD). In the previously proposed BDD SFQ logic circuits, we have used one-to-two binary switches as a node cell in a BDD tree. In this study we will propose a new implementation method of SFQ BDD circuits, in which two nodes are implemented by using a 2-input 2-output switch gate. By employing the new approach, we have designed and implemented a one-bit full adder using the NEC 2.5 kA/cm2 Nb standard process and the CONNECT cell library. The maximum operating frequency of the full adder was found to be 40 GHz by circuit simulations and 32.8 GHz by on-chip high-speed tests.
Keywords :
adders; binary decision diagrams; circuit simulation; integrated circuit design; superconducting device testing; superconducting logic circuits; superconducting switches; 2-input 2-output switch gate; 32.8 GHz; 40 GHz; BDD SFQ logic circuits; BDD tree; CONNECT cell library; NEC 2.5 kA/cm Nb standard process; asynchronous circuit; binary decision diagram; binary switches; circuit simulations; design methodology; dual rail; maximum operating frequency; node cell; on-chip high-speed tests; one-bit full adder; superconducting circuit; Adders; Binary decision diagrams; Boolean functions; Circuit testing; Data structures; Design methodology; Logic circuits; National electric code; Switches; Switching circuits; Adder; BDD; SFQ logic circuit; asynchronous circuit; binary decision diagram; dual rail; superconducting circuit;
Journal_Title :
Applied Superconductivity, IEEE Transactions on
DOI :
10.1109/TASC.2005.849855
