DocumentCode
834595
Title
Testing of a NORA CMOS serial-parallel multiplier
Author
Bayoumi, Magdy A. ; Ling, Nam
Author_Institution
Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA
Volume
24
Issue
2
fYear
1989
fDate
4/1/1989 12:00:00 AM
Firstpage
494
Lastpage
503
Abstract
The NORA-CMOS (no-race complementary metal-oxide-silicon) serial-parallel multiplier presented here is testable. Error detection is achieved at two levels: online functional testing and offline structural testing. Functional testing uses low-cost residue codes to detect errors at the overall level. Modulus is adopted as the check base. For structural testing, a NORA CMOS circuit error detection technique proposed based on the structure, properties, and operations of NORA CMOS is used. The proposed technique can detect output stuck-at, stuck-open, and stuck-on faults. Such a two-level testing strategy reduces test time and chip area overhead, identifies faulty locations, and has the ability to detect both transient and permanent faults.<>
Keywords
CMOS integrated circuits; automatic testing; digital arithmetic; error detection; fault location; integrated circuit testing; integrated logic circuits; logic testing; multiplying circuits; CMOS; NORA; error detection technique; faulty locations; low-cost residue codes; no race circuit; offline structural testing; online functional testing; permanent faults; race free operation; serial-parallel multiplier; stuck-at; stuck-on faults; stuck-open; testable design; transient faults; two-level testing strategy; CMOS technology; Circuit testing; Digital signal processing; Digital signal processing chips; Integrated circuit technology; Pins; Silicon; System testing; Throughput; Very large scale integration;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.18615
Filename
18615
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