DocumentCode
834608
Title
Complete Monte Carlo model description of lumped-element RSFQ logic circuits
Author
Fourie, Coenrad Johann ; Perold, Willem Jakobus ; Gerber, Hendrik Retief
Author_Institution
Dept. of Electr. & Electron. Eng., Univ. of Stellenbosch, Matieland, South Africa
Volume
15
Issue
2
fYear
2005
fDate
6/1/2005 12:00:00 AM
Firstpage
384
Lastpage
387
Abstract
Over the last decade, Monte Carlo simulations have emerged as the most useful way of predicting the yield of RSFQ circuits, as they consider all manufacturing tolerance effects on a circuit, and are not restricted to bias current variations. Here we finally present a comprehensive definition of layout-extracted Monte Carlo model creation for lumped-element Spice simulations-from the local and global values for inductance, resistance and junction area from statistical models, to the inclusion of parasitics, layer-to-layer variations, variations in the penetration depth, and capacitance and mutual coupling. Finally, the addition of bias current trimming to the simulations to compensate for most global variations is described, and comparative yield results listed.
Keywords
Monte Carlo methods; SPICE; circuit simulation; integrated circuit layout; integrated circuit modelling; superconducting logic circuits; Monte Carlo model description; Monte Carlo simulations; RSFQ circuit models; Spice models; bias current trimming; bias current variations; comparative yield results; junction area; layer-to-layer variations; layout extraction; lumped-element RSFQ logic circuits; lumped-element Spice simulations; manufacturing tolerance effects; mutual coupling; penetration depth; statistical models; yield prediction; Circuit optimization; Circuit simulation; Circuit testing; Inductance; Logic circuits; Manufacturing processes; Monte Carlo methods; Parasitic capacitance; Predictive models; Virtual manufacturing; Layout extraction; Monte Carlo models; RSFQ circuit models; Spice models; yield prediction;
fLanguage
English
Journal_Title
Applied Superconductivity, IEEE Transactions on
Publisher
ieee
ISSN
1051-8223
Type
jour
DOI
10.1109/TASC.2005.849856
Filename
1439656
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