RSFQ digital signal processor for interference cancellation

Author

Kataeva, Irina ; Zhao, Hongxia ; Engseth, Henrik ; Tolkacheva, Elena ; Kidiyarova-Shevchenko, Anna

Author_Institution

Microtechnology & Nanoscience Dept., Chalmers Univ. of Technol., Gothenburg, Sweden

Volume

15

Issue

2

fYear

2005

fDate

6/1/2005 12:00:00 AM

Firstpage

405

Lastpage

410

Abstract

RSFQ high performance digital signal processor capable to perform up to 13 13-bit fixed-point GMACS has been designed for use in successive interference canceller in W-CDMA wireless systems. The performance of the processor has been verified by numerical simulations and VHDL simulation using accurate modeling of the RSFQ gates. Components of the processor, 4 × 4 and 5 × 5 parallel multipliers, 4 × 5, 20 × 5 and 4 × 15 parallel shift registers have been designed and experimentally tested.

Keywords

code division multiple access; digital signal processing chips; interference suppression; multiplying circuits; radiofrequency interference; shift registers; superconducting logic circuits; superconducting processor circuits; 13 bit; 13-bit fixed-point GMACS; RSFQ gates; RSFQ high performance digital signal processor; VHDL simulation; W-CDMA wireless systems; interference cancellation; multiply-accumulate unit; numerical simulations; parallel multipliers; parallel shift registers; radiofrequency interference; successive interference canceller; Clocks; Digital signal processing; Digital signal processors; Interference cancellation; Multiaccess communication; Prototypes; Shift registers; Signal design; Silicon carbide; Vectors; Multiply-Accumulate Unit; RSFQ; successive interference canceller;

fLanguage

English

Journal_Title

Applied Superconductivity, IEEE Transactions on

Publisher

ieee

ISSN

1051-8223

Type

jour

DOI

10.1109/TASC.2005.849861

Filename

1439661