Title :
Frequency multiply circuit for superconducting A/D converter
Author :
Yoshida, A. ; Hirano, S. ; Suzuki, H. ; Hasuo, S. ; Tanabe, K. ; Ito, T. ; Himi, T. ; Takai, H.
Author_Institution :
Supercond. Res. Lab., Tokyo, Japan
fDate :
6/1/2005 12:00:00 AM
Abstract :
A new frequency multiply circuit generating a 20 GHz sampling clock from an external 5 GHz signal for a lowpass sigma-delta modulator was proposed and designed. The multiply circuit was composed of a ladder circuit, a modified Josephson transmission line (JTL) and T-flip flop (T-FF). We confirmed by numerical simulation that the period jitter of SFQ pulse trains generated by the ladder circuit could be reduced to a value small enough to realize 14-bit resolution for 10 MHz bandwidth by utilizing the repulsion effect between SFQ pulses in the modified JTL. The multiply circuit was fabricated by a 2.5 kA/cm2 Nb process, and its correct operation was confirmed.
Keywords :
Josephson effect; flip-flops; frequency multipliers; integrated circuit design; ladder networks; low-pass filters; multiplying circuits; sigma-delta modulation; superconducting junction devices; superconducting transmission lines; 10 MHz bandwidth; 14 bit; 14-bit resolution; 20 GHz; 20 GHz sampling clock; 5 GHz; Josephson device; Josephson transmission line; SFQ pulse trains; SFQ pulses; T-flip flop; frequency multiply circuit; ladder circuit; lowpass sigma-delta modulator; numerical simulation; period jitter; rapid single flux quantum circuit; repulsion effect; superconducting A/D converter; Clocks; Delta-sigma modulation; Distributed parameter circuits; Frequency conversion; Numerical simulation; Pulse circuits; Sampling methods; Signal design; Signal generators; Superconducting transmission lines; Analog-to-digital converter; Josephson device; frequency multiply circuit; rapid single flux quantum circuit; sigma-delta modulator;
Journal_Title :
Applied Superconductivity, IEEE Transactions on
DOI :
10.1109/TASC.2005.849867
