• DocumentCode
    835254
  • Title

    SJ-LDMOS with high breakdown voltage and ultra-low on-resistance

  • Author

    Chen, W. ; Zhang, B. ; Li, Z.

  • Author_Institution
    Center of IC Design, Univ. of Electron. Sci. & Technol. of China, Chengdu Sichuan
  • Volume
    42
  • Issue
    22
  • fYear
    2006
  • Firstpage
    1314
  • Lastpage
    1315
  • Abstract
    A new design concept is proposed to eliminate the substrate-assisted depletion effect in a super-junction (SJ) LDMOS. The key feature of the concept is that a non-uniform N-buried layer is implemented which compensates for the charge interaction between the P-substrate and SJ region, realising high breakdown voltage (>700 V) and ultra-low on-resistance. Furthermore, the proposed device is compatible with smart power technology
  • Keywords
    MOSFET; semiconductor device breakdown; semiconductor device reliability; P-substrate; TV-buried layer; breakdown voltage; smart power technology; substrate-assisted depletion effect; super-junction LDMOS; super-junction region;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20062751
  • Filename
    4015938
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=835254